1. Field of the Invention
The present invention relates generally to signal processing, and specifically to signal processing in which symbol samples for delay locked loop processing are extracted pre and post correlator processing.
2. Description of Related Art
In a wideband Code Division Multiple Access (CDMA) system, multiple paths of a transmitted signal can be tracked using a rake receiver implemented at a base station due to the nature of spread spectrum sequences in a wireless channel. The rake receiver functions as several receivers operating with associated propagation delays based on the respective delays experienced by arriving multipath signals. The rake receiver has a tracking loop for each rake finger of a user that tracks the movement of the fingers typically through the use of a delay locked loop (DLL). The DLL, which computes the error in, and subsequently shifts, the sample time, needs to be performed on a per finger, or multipath, basis.
To compute the error in the sample time, the DLL requires early and late sample times. Specifically, the DLL takes the early and late samples for a given multipath signal being tracked and calculates the energy for the early and late correlations. The difference between these two energies is multiplied by a pre-computed gain factor to obtain a timing correction. A third ontime sample sequence is used for demodulation purposes as it has the largest signal to noise ratio.
In conventional DLLs, interpolators provide the early, late and ontime samples so that three samples are provided for each CDMA symbol. A conventional hardware implementation often processes the early and late correlation outputs in parallel. As the data resulting from the early and late correlations is processed using dedicated links, transfer bandwidth is not a problem.
In new high end devices, more processing is being moved to digital signal processors. In addition, the potential for performance improvements via more sophisticated software algorithms creates motivation to place more functions like DLL processing in software. However, this shift in processing puts a strain on Digital Signal Processor (DSP) bandwidth, as such bandwidth is typically small enough to create processing bottlenecks at the DSP I/O interface and therefore slow down DSP processing times.
Clearly a need exists for more efficient signal processing systems for, for example, delay locked loops.